As one of problems in an information processing device, of which high availability of a system is sought, such as a server of a backbone system, a bit error countermeasure with respect to a soft error of a memory, for example, may be cited. Such information processing device employs an error check and correct (ECC) memory which includes an error detecting and correcting function as a countermeasure with respect to system down caused by a bit error of a memory. Upon occurrence of a bit error of a memory, the ECC memory is capable of detecting an occurrence position of the bit error and correcting the erroneous bit.
Further, in an information processing device such as a server in recent years, a management controller or the like monitors an error notification register of a memory in a memory controller. For example, a management controller counts the number of times of an occurrence of a bit error of a memory by using an error notification register of a memory. Further, the management controller has a mechanism to report as a failure of a memory when the number of times of an occurrence of a bit error exceeds a threshold value.
As a testing method of an ECC memory, the following test has been employed in the related arts, for example.
(1) A test for executing writing and reading of data by using various data patterns such as a crosstalk noise pattern.
(2) A test for specifying a memory block unit suitable for high-speed memory access by a cache on the basis of a cache size of a CPU which performs memory access, so as to execute moving or copying of data in the specified memory block unit.                (3) A test for performing quality determination of a memory on the basis of presence/absence of an occurrence of an uncorrectable error after the above-mentioned tests of (1) and (2) and the like. An uncorrectable error indicates, for example, bit errors the number of which exceeds the number of bits that are error correctable.        
(4) A test for performing quality determination of a memory on the basis of whether or not frequency of occurrence of bit errors exceeds a threshold value, after the above-mentioned tests of (1) and (2) and the like.
In the related arts, quality has been maintained by repeatedly performing the tests illustrated in the above procedure with respect to test objects of all memory cells and memory addresses within a predetermined time period.
International Publication Pamphlet No. WO 2008/047443, Japanese Laid-open Patent Publication No. 6-208799, and Japanese Laid-open Patent Publication No. 61-131050 are examples of the related arts.